Liquid crystal displays (LCDs), such as thin film transistor LCDs, are increasingly being used in electronic devices, such as in mobile phones. One design constraint on the use of LCDs is their ability to provide sufficiently compact and low-cost displays capable of clearly displaying moving images. New controllers have emerged that are targeted at specifically controlling the display of moving images on LCDs. However, these specialized controllers may be prohibitively expensive for use in some electronic devices, such as in some mobile phones. Moreover, the display architecture may require the use of a conventional controller along with the specialized controller. The use of two controllers may lead to the use of interrupt-based processing for large amounts of image data, which may decrease the efficiency at which moving images are processed and may increase the complexity of the control software.
FIG. 1A illustrates a conventional LCD device 100. Referring to FIG. 1A, the LCD device 100 includes an LCD panel 101, an LCD driver 110, and a controller 120.
The controller 120 controls the display of image data on the LCD panel 101. The controller 120 generates and outputs control signals, which can include a chip selection “CS” signal, a write clock “WR” signal, a DATA signal, and the like.
The CS signal is used to select and enable individual pixels on the LCD panel 101. The WR signal is used to write data (e.g., image data), which is received from circuitry external to the LCD device 100, to a memory 113 included in the LCD driver 110. Hereinafter, the write clock signal will be referred to as CLK_W. The DATA signal refers to image data that is generated from data that is received from circuitry that is external to the LCD device 100.
The LCD driver 110 includes a source driver/gate driver 111, the memory 113, and an oscillator 115.
The image data from the controller 120 is written into the memory 113. The write operation is performed using the write clock signal CLK_W which is output by the controller 120, and which may be used as an internal operational clock for the controller 120.
The source driver/gate driver 111 reads the image data from the memory 113 and outputs therefrom an image signal to the LCD panel 101 in response to a control signal which is generated by the controller 120.
The source driver/gate driver 111 also responds to the control signal transmitted from the controller 120 by controlling positioning of the image signal on the LCD panel 101. Such structure and operation of the source driver/gate driver 111 is well known to those of ordinary skill in the art and, accordingly, further details thereof will be omitted for brevity.
The oscillator 115 generates a scan clock signal CLK_FLM which is used by the LCD driver 110 to scan an image signal from the source driver/gate driver 111 onto the display of the LCD panel 101. The scanning operation using the scan clock signal CLK_FLM will be described with reference to FIG. 1B.
FIG. 1B is a timing diagram that illustrates relative timing between the write clock signal CLK_W and the scan clock signal CLK_FLM and operation thereof, and further illustrates a tearing effect that occurs during the operation of the LCD device 100.
In the conventional LCD device 100 of FIG. 1A, the write clock signal CLK_W, used for regulating writing of image data into the memory 113, and the scan clock signal CLK_FLM, used to scan image data on the display of the LCD panel 101, are not synchronized to one another.
Referring to FIG. 1B, when the scan clock signal CLK_FLM is low, the image signal is scanned to pixels in the LCD panel 101. A bottom pixel line is referred to as Line 1 and a top pixel line is referred to as Line 160. When the scan clock signal CLK_FLM generated by the oscillator 115 is low, the LCD driver 110 performs a scanning operation from Line 1 of the LCD panel 101 up to Line 160 of the LCD panel 101.
When the write clock signal CLK_W is low, the image data transmitted by the controller 120 is written to the memory 113. The write operation is performed in units of frame data. In other words, the image data is written during the low level period of the write clock signal CLK_W and single frame data is written to the memory 113 during a single interval of the low level period. For reference, a general scan clock signal CLK_FLM can have a frequency of 60 Hz and a general write clock signal CLK_W can have a frequency band of 15-30 Hz. Thus, when the scanning operation is performed three or four times, the write operation is performed once. When new image data is not input, the LCD driver 110 scans stored image data and displays the image data on the LCD panel 101.
In the LCD device 100, the write clock signal CLK_W and the scan clock signal CLK_FLM are not synchronized with each other. Moreover, the duration of the low level period of the write clock signal CLK_W can be constant, and an operating frequency band and an active period are not matched. Consequently, at a point “a” in FIG. 1B, the write clock signal CLK_W and the scan clock signal CLK_FLM, overlap each other at timing coordinates (a, X).
FIG. 1C illustrates an image that is displayed on the LCD panel 101 and which exhibits a tearing effect as a result of the relative signal timing shown in FIG. 1B.
Before time “a”, the LCD driver 110 scans the image data that was previously stored in the memory 113. However, after time “a”, the LCD driver 110 scans image data that is newly stored in the memory 113 after the time “a”. In the example of FIG. 1C, the LCD driver 110 displays white pixel color from Line 1 to a line X in response to the image data that was stored in the memory 113 before time “a”, and displays black pixel color from the line X to Line 160 in response to other image data that was stored in the memory 113 after time “a”.
Accordingly, a tearing effect in the displayed image occurs at the line X of the LCD panel 101. The tearing effect corresponds to a lack of logical association among image data that is displayed on the LCD panel 101. In the present example, the white pixels are associated with the same image, however the black pixels are associated with another image that is intended to displayed subsequent to the display of the white image. The timing intersection of the scan clock signal CLK_FLM and the write clock signal CLK_W corresponds to the location of the tearing effect on the image that is displayed on the LCD device 101.
FIG. 2A illustrates a conventional LCD device 200 device that is configured to attempt to prevent the occurrence of a tearing effect.
The LCD device 200 includes an LCD panel 201, an LCD driver 210, and a controller 220, which can be configured to operate in a similar manner to the LCD panel 101, the LCD 110, and the controller 120 described above, and, accordingly, further description of these components is omitted for brevity.
In an attempt to prevent a tearing effect in a displayed image, the LCD device 200 includes a synchronization processing unit 222 in the controller 220. The operation of the synchronization processing unit 222 will be described in detail with reference to FIG. 2B.
FIG. 2B is a block diagram that illustrates various operations of the controller 220 and the LCD driver 210.
Referring to FIG. 2B, the controller 220 of the LCD device 200 receives a signal FLM_Vsync providing synchronization information for a scan clock signal from the LCD driver 210. The synchronization processing unit 222 of the controller 220 is configured to synchronize the write clock signal CLK_W with the scan clock signal CLK_FLM using the received signal FLM_Vsync. The synchronization processing unit 222 synchronizes the scan clock signal CLK_FLM and the write clock signal CLK_W in response to each transition of the write clock signal CLK_W from high to low.
In the conventional LCD devices 100 and 200 illustrated in FIG. 1A and FIG. 2A, the controllers 120 and 220 cannot perform other operations (i.e., stop carrying-out other operations) while they process image data. Because other operations are interrupted while image data is processed, the processing can be referred to as interrupt processing.
If such interrupt processing is to be avoided, thereby avoiding interruption of other operations in response to the input of a signal FLM, the LCD device 200 illustrated in FIG. 2A can include a separate processor that is configured to synchronize the write clock signal CLK_W in response to the input signal FLM_Vsync. The separate processor may be included in the synchronization processing unit 222 of the LCD device 200.
FIG. 2C is a timing diagram illustrates relative timing between the write clock signal CLK_W and the scan clock signal CLK_FLM during the operation of the LCD device 200 of FIG. 2A. Referring to FIG. 2C, when the write clock signal CLK_W is synchronized with the scan clock signal CLK_FLM, an intersecting point “a” between such signals described in FIG. 1B does not occur and, therefore, occurrence of the tearing effect may thereby be reduced.
Although the tearing effect is reduced, the inventors of the present application have determined that the tearing effect may not be completely prevented, possibly because of a change in the operating frequency of the scan clock signal CLK_FLM and/or dispersion of the write clock signal CLK_W generated by the controller 220.
As described above, in the conventional LCD device 100, the scan clock signal CLK_FLM and the write clock signal CLK_W are not synchronized with each other and the write speed of the write clock signal CLK_W is constant, which results in occurrence of the tearing effect.
Moreover, although the LCD device 200 can reduce the occurrence of the tearing effect, the synchronization processing unit 220 needs to have a separate processor that carries out the signal synchronization. Furthermore, the tearing effect may not be completely prevented, possibly because of changes in the operating frequency of the scan clock signal CLK_FLM and/or dispersion of the write clock signal CLK_W generated by the controller 220.